AN1050/1098 1/9 application note input capture with st62 16-bit auto-reload timer by 8-bit micro application team 1 introduction this note presents how to use the st62 16-bit auto-reload timer (artimer) to measure du- rations or frequencies of an input signal. an example shows how to capture an input signal to make an output signal with the same frequency as input signal but with a duty cycle equal to 50%. 1.1 16 bit auto-reload timer description this timer is a 16-bit downcounter timer with prescaler (see figure 1. ). it includes auto-reload pwm, capture and compare capability with two input(cp1,cp2) and two output pins(ovf,pwm). it is controlled by the following registers (8 bit): C status control registers (scr1, scr2, scr3, scr4) C capture register high (cph) and low (cpl). for the total 16-bit the register is cp. C mask register high (maskh) and low (maskl). for the total 16-bit the register is mask. C decremental counter register (tc with 16-bit) C compare register high (cmph) and low (cmpl). for the total 16-bit the register is cmp. C reload/capture register high (rlcph) and low (rlcpl). for the total 16-bit the register is rlcp. 1
introduction 2/9 the prescaler ratio can be programmed to choose the timer input frequency f int (see table 1 ). figure 1. 16-bit auto-reload timer block diagram scr1 scr2 scr3 scr4 8 8 8 8 16 16 16 16 cmp mask rlcp cp compare compare tc to 0 16 16 16 16 8 psc ratio f int control logic int 8-bit mcu data bus bus interface 16-bit data bus cp2 cp1 ovf pwm f osc
3/9 introduction 1.2 capture mode this can be used to measure time duration or frequencies (see figure 2. ).this mode is used to measure the time elapsed between two edges of one or two external signal. each edge could be rising or falling depend on initialisation. with the 16-bit tc downcounter and with f osc to 8mhz, a signal of 4ms duration can be meas- ured with a resolution of 1/32768. example : let's measure the time elapsed between two rising edges on cp2: the 16-bit cp value contains the time between the two cp2 rising edges and will be divided by two to be loaded in the 16-bit cmp register. the capture mode uses the cp2 triggered restart mode with cp2 event detection (rdsel2=1, rdsel1=0 of scr2 register). its mean that each cp2 edge sets off the capture of the tc value in the cp register and then reloads tc register with the rlcp value. the cp2 interrupt is enabled (cp2ien=1 of scr3 register) and cmp interrupt is enabled (cmpien=1 of scr3 register) to manage the output bit pa2. in the cp2 interrupt sub-program the output bit pa2 is set to 1. in the cmp interrupt sub-pro- gram the output bit pa2 is set to 0. the main program calculates the division by 2 of the captured 16-bit value and saves it in newcmph and newcmpl. the prescaler ratio must be programmed according to the expected duration to measure. in this example it is programmed to: prescaler ratio = 16, clock source = f osc = 8mhz. the period to measure must be in the range of 250s to 133ms. the sharing of a 16-bit data between the main program and the interrupt sub-program obliges to disable the interruption for each handling of this data in the main program. this causes a jit- ters of up to 30s. the delay between the input signal active edge and the output signal is of 36s. the rlcp register is load with ffffh to avoid subtraction to calculate the delay between the cp2 edge and the compare value reached by the tc value. table 1. prescaler programming ratio psc2 psc1 prescaler ratio 0 0 clock disabled 01 1 10 4 11 16
introduction 4/9 figure 2. tc, cp and cmp value evolution synchronized with the input cp2. tc register 0 t pa2 bit ouput t mask&tc=mask&cmp cp value cmp value= cp2 t previous cp value divide by 2 capture reload
5/9 introduction program example ;*************************************************************************** ;*****************st6230 auto-reload 16-bit capture mode ****************** ;*** ;*** object: give an output ttl square siqnal at the same frequency ;*** of the no symmetrical ttl input signal ;*** ;*** input : ttl signal in the range of 7.5hz to 4000hz on cp2 ;*** ;*** output: ttl signal with the same frequency of cp2 but with ;*** a duty cycle of 50%. the signal has a delay of 36s ;*** and a jitters of 30s with a clock frequency of 8mhz. ;*** ;*** author: jean-luc crebouw ;*** ;*************************************************************************** .vers "st6230" .romsize 8 ;*** data registers *** .input "623x.asm" ;*** data ram *** templ .def 084h ; low byte of the divider by two temph .def 085h ; high byte of the divider by two newcmpl.def 086h ; low byte of the result divider newcmph.def 087h ; high byte of the result divider data .def 088h ; data copy of the a port save_cpl.def 089h ; save the cp hight save_cph.def 08ah ; save the cp low ;*************************** initialization ********************************* .org 800h reset reti ;*** art16 initialisation *** ldi scr1,0f0h ; prescal by 16 to have f int =.5 mhz ; reload mode ; runres ; no interrupt with overflow ; reset mode for ovfmd ldi scr2,02h ; cp1 input interrupt disable ; cp2 triggered restart mode with cp2 event ; detection ldi scr3,0d0h ; cp2 polarity with rising edge
introduction 6/9 ; cp2 interrupt enable ; compare interrupt enable ; compare to zero interrupt disable ldi scr4,0h ; overflow output disable ;pwm output disable ldi rlcph,0ffh ; rlcp register to ffffh ldi rlcpl,0ffh ; ldi cmph,0ffh ; cmp register to ff00h ldi cmpl,000h ; ldi maskh,0ffh ; mask = 0ffffh ldi maskl,0ffh ;*** porta initialisation for output bit 2 and cp2 input ldi ddra,04h ldi ora,04h clr a ld data,a ; data = 0 ;*** general interrupt *** ldi ior,10h ;enables all interrupts. ;*************************************************************************** ;*****************************main program******************************** ;***********divide the cp value by two to load cmp register with ********** pulse: ;*** read the previous capture out of interrupt to avoid save_cpl ;*** and save_cph from a different cp value ldi ior,00h ; disables all interrupts. ld a,save_cpl ld templ,a ld a,save_cph ldi ior,10h ; enables all interrupts. ld temph,a ;*** divide by two temp (16-bit) clr a ld a,templ rlc a rlc a rlc a rlc a rlc a rlc a rlc a rlc a ld templ,a clr a ld a,temph
7/9 introduction rlc a rlc a rlc a rlc a rlc a rlc a rlc a rlc a ld temph,a jrnc no_1 ld a,templ addi a,080h ld templ,a no_1: ld a,temph addi a,080h ld temph,a ld a,templ ;*** store the next cmp value out of interrupt ldi ior,00h ; disables all interrupts. ld newcmpl,a ld a,temph ld newcmph,a ldi ior,10h ; enables all interrupts. jp pulse ;**************************end of main program**************************** ;*************************************************************************** ;**************************uart it management***************************** it_uart: ld x,a ; save a ;*** if compare interrupt jrs 5,scr3,it_cp2 ld a,data ; output port pa2 = 0 ld dra,a set 2,data ; data bit 2 = 1 res 3,scr3 ; reset cmpflg ld a,x ; restore a reti it_cp2: ;*** else cp2 interrupt ld a,data ; output port pa2 = 1 ld dra,a res 2,data ; data bit 2 = 0 res 5,scr3 ; reset cp2flg
introduction 8/9 res 5,scr2 ; reset cp2err ld a,cph ; read cp register and save the 16-bit value ld save_cph,a ; in save_cph and save_cpl ld a,cpl ld save_cpl,a ld a,newcmph ld cmph,a ; store newcmph and newcmpl in cmp to have ld a,newcmpl ; cmp = previous cp / 2 ld cmpl,a ld a,x ; restore a reti ;***********************end of uart it management************************* ;*************************************************************************** ;******************** restart and interrupt vectors ************************ .org 0ff0h reti ; ff0h reti jp it_uart ; ff2h reti ; ff4h reti reti ; ff6h reti .org 0ffch nmi nop reti res jp reset
9/9 introduction "the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products." information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com
|
